(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to fabricate a bipolar--complimentary metal oxide semiconductor, (BiCMOS), device, on a semiconductor substrate.
(2) Description of Prior Art
The addition of bipolar junction transistors, to CMOS designs, results in a BiCMOS device, superior in performance to CMOS counterparts, as a result of the inclusion of the higher performing bipolar junction devices. An objective of the semiconductor industry has been to develop a process fabrication sequence, that allows integration of the bipolar, and CMOS devices, using shared process steps, and without sacrificing the performance of the bipolar junction transistor, as a result of having to use basically CMOS materials and processes.
This invention will describe a process for fabricating a BiCMOS device, in which a novel twin well, and epitaxial silicon layer, are featured, to arrive at a BiCMOS chip, formed using many shared, (bipolar and CMOS), process steps, and formed using an N type epitaxial layer, at a concentration, that allows the bipolar device, to achieve the desired performance requirements. Prior art, such as Ronkainen et al, in U.S. Pat. No. 5,776,807, describes a process for the fabricating a BiCMOS device, however this prior art does not describe the integration of the N type epitaxial layer, using a specific dopant level, needed to optimize bipolar performance, described in this present invention.